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single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers ?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 ja n uary 2011 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 high speed 10mbit/s logic gate optocouplers features ve ry high speed ?10 mbit/s superior cmr ?10 kv/? double working voltage-480v f an-out of 8 over -40? to +85? logic gate output strobable output wired or-open collector u .l. recognized (file # e90700) applications ground loop elimination lsttl to ttl, lsttl or 5-volt cmos line receiver, data transmission data multiplexing switching power supplies pulse transformer replacement computer-peripheral interface description the 6n137, hcpl2601, hcpl2611 single-channel and hcpl2630, hcpl2631 dual-channel optocouplers consist of a 850 nm algaas led, optically coupled to a ve ry high speed integrated photo-detector logic gate with a strobable output. this output features an open collec- tor, thereby permitting wired or outputs. the coupled parameters are guaranteed over the temperature range of -40? to +85?. a maximum input signal of 5ma will provide a minimum output sink current of 13ma (fan out of 8). an internal noise shield provides superior common mode rejection of typically 10kv/?. the hcpl2601 and hcpl2631 has a minimum cmr of 5kv/?. the hcpl2611 has a minimum cmr of 10kv/?. schematics package outlines 8 1 8 1 8 1 a 0.1? bypass capacitor must be connected between pins 8 and 5 (1) . 1 2 3 4 5 6 7 8 n/c _ v cc v e v o gnd + n/c v f 1 2 3 4 5 6 7 8 + _ v f1 v cc v 01 v 02 gnd v f2 _ + hcpl2630 hcpl2631 6n137 hcpl2601 hcpl2611 t ruth table (positive logic) input enable output h h l l h h h l h l l h h nc l l nc h
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 2 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers absolute maximum ratings (t a = 25? unless otherwise speci?d) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. *for peak soldering re?w, please refer to the re?w pro?e on page 11. recommended operating conditions the recommended operating conditions table de?es the conditions for actual device operation. recommended operating conditions are speci?d to ensure optimal performance to the datasheet speci?ations. fairchild does not recommend exceeding them or designing to absolute maximum ratings. *6.3ma is a guard banded value which allows for at least 20% ctr degradation. initial input current threshold value is 5.0ma or less. symbol parameter value units t stg storage temperature -55 to +125 ? t opr operating temperature -40 to +85 ? t sol lead solder temperature (for wave soldering only)* 260 for 10 sec ? emitter i f dc/average forward single channel 50 ma input current dual channel (each channel) 30 v e enable input voltage not to exceed v cc by more than 500mv single channel 5.5 v v r reverse input voltage each channel 5.0 v p i po w er dissipation single channel 100 mw dual channel (each channel) 45 detector v cc (1 minute max) supply voltage 7.0 v i o output current single channel 50 ma dual channel (each channel) 50 v o output voltage each channel 7.0 v p o collector output single channel 85 mw po w er dissipation dual channel (each channel) 60 symbol parameter min. max. units i fl input current, low level 0 250 ? i fh input current, high level *6.3 15 ma v cc supply voltage, output 4.5 5.5 v v el enable voltage, low level 0 0.8 v v eh enable voltage, high level 2.0 v cc v t a low level supply current -40 +85 ? nf an out (ttl load) 8
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 3 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers electrical characteristics (t a = 0 to 70? unless otherwise speci?d) individual component characteristics switching characteristics (t a = -40? to +85?, v cc = 5v, i f = 7.5ma unless otherwise speci?d) symbol parameter test conditions min. typ.* max. unit emitter v f input forward voltage i f = 10ma 1.8 v t a = 25? 1.4 1.75 b vr input reverse breakdown v oltage i r = 10? 5.0 v c in input capacitance v f = 0, f = 1mhz 60 pf ? v f / ? t a input diode temperature coefcient i f = 10ma -1.4 mv/? detector i cch high level supply current v cc = 5.5v, i f = 0ma, v e = 0.5v single channel 7 10 ma dual channel 10 15 i ccl low level supply current single channel v cc = 5.5v, i f = 10ma 913ma dual channel v e = 0.5v 14 21 i el low level enable current v cc = 5.5v, v e = 0.5v -0.8 -1.6 ma i eh high level enable current v cc = 5.5v, v e = 2.0v -0.6 -1.6 ma v eh high level enable voltage v cc = 5.5v, i f = 10ma 2.0 v v el low level enable voltage v cc = 5.5v, i f = 10ma (3) 0.8 v symbol ac characteristics test conditions min. typ.* max. unit t plh propagation delay time to output high level r l = 350 ? , c l = 15pf (4) (fig. 12) t a = 25? 20 45 75 ns 100 t phl propagation delay time to output low level t a = 25? (5) 25 45 75 ns r l = 350 ? , c l = 15pf (fig. 12) 100 |t phl ? plh | pulse width distortion (r l = 350 ? , c l = 15pf (fig. 12) 3 35 ns t r output rise time (10?0%) r l = 350 ? , c l = 15pf (6) (fig. 12) 50 ns t f output rise time (90?0%) r l = 350 ? , c l = 15pf (7) (fig. 12) 12 ns t elh enable propagation delay time to output high level i f = 7.5ma, v eh = 3.5v, r l = 350 ? , c l = 15pf (8) (fig. 13) 20 ns t ehl enable propagation delay time to output low level i f = 7.5ma, v eh = 3.5v, r l = 350 ? , c l = 15pf (9) (fig. 13) 20 ns |cm h | common mode tr ansient immunity (at output high level) t a = 25?, |v cm | = 50v (peak), i f = 0ma, v oh (min.) = 2.0v, r l = 350 ? (10) (fig. 14) 6n137, hcpl2630 10,000 v/? hcpl2601, hcpl2631 5000 10,000 |v cm | = 400v hcpl2611 10,000 15,000 v/? |cm l | common mode tr ansient immunity (at output low level) r l = 350 ? , i f = 7.5ma, v ol (max.) = 0.8v, t a = 25? (11) (fig. 14) 6n137, hcpl2630 10,000 hcpl2601, hcpl2631 5000 10,000 |v cm | = 400v hcpl2611 10,000 15,000
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 4 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers electrical characteristics (continued) t ransfer characteristics (t a = -40 to +85? unless otherwise speci?d) isolation characteristics (t a = -40? to +85? unless otherwise speci?d.) *all typicals at v cc = 5v, t a = 25? notes: 1. the v cc supply to each optoisolator must be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package v cc and gnd pins of each device. 2. each channel. 3. enable input ?no pull up resistor required as the device has an internal pull up resistor. 4. t plh ?propagation delay is measured from the 3.75ma level on the high to low transition of the input current pulse to the 1.5 v level on the low to high transition of the output voltage pulse. 5. t phl ?propagation delay is measured from the 3.75ma level on the low to high transition of the input current pulse to the 1.5 v level on the high to low transition of the output voltage pulse. 6. t r ?rise time is measured from the 90% to the 10% levels on the low to high transition of the output pulse. 7. t f ?fall time is measured from the 10% to the 90% levels on the high to low transition of the output pulse. 8. t elh ?enable input propagation delay is measured from the 1.5v level on the high to low transition of the input voltage pulse to the 1.5v level on the low to high transition of the output voltage pulse. 9. t ehl ?enable input propagation delay is measured from the 1.5v level on the low to high transition of the input voltage pulse to the 1.5v level on the high to low transition of the output voltage pulse. 10. cm h ?the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., v out > 2.0v). measured in volts per microsecond (v/?). 11. cm l ?the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., v out < 0.8v). measured in volts per microsecond (v/?). 12. device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted together. symbol dc characteristics test conditions min. typ.* max. unit i oh high level output current v cc = 5.5v, v o = 5.5v, i f = 250?, v e = 2.0v (2) 100 ? v ol low level output current v cc = 5.5v, i f = 5ma, v e = 2.0v, i cl = 13ma (2) .35 0.6 v i ft input threshold current v cc = 5.5v, v o = 0.6v, v e = 2.0v, i ol = 13ma 3 5 ma symbol characteristics test conditions min. typ.* max. unit i i-o input-output insulation leakage current relative humidity = 45%, t a = 25?, t = 5s, v i-o = 3000 vdc (12) 1.0* ? v iso withstand insulation test v oltage rh < 50%, t a = 25?, i i-o 2?, t = 1 min. (12) 2500 v rms r i-o resistance (input to output) v i-o = 500v (12) 10 12 ? c i-o capacitance (input to output) f = 1mhz (12) 0.6 pf
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 5 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers t ypical performance curves fig.1 low level output voltage vs. ambient temperature t a ?ambient temperature ( c) t a ?ambient temperature ( c) t a ?ambient temperature ( c) -40 -20 0 20 40 60 80 v ol ?low level output vo ltage (v) t p ?propagation de lay (ns) i f ?forward current (ma) i ol low level output curr ent (ma) v o output voltage (v) i f forward current (ma) i f - forward current (ma) i ol = 16ma fig. 4 low level output current vs. ambient temperature -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 i f = 5ma i f = 10ma i f = 15ma fig. 5 input threshold current vs. ambient temperature i ft ?input threshold current (ma) r l = 350 ? r l = 1k ? r l = 4k ? fig. 6 output voltage vs. input forward current r l = 350 ? r l = 1k ? r l = 4k ? i ol = 6.4ma i ol = 9.6ma i ol = 12.8 ma conditions: i f = 5 ma v e = 2 v v cc = 5.5v conditions: v cc = 5.0 v v o = 0.6 v fig. 2 input diode forward voltage vs. forward current v f ?forward voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 conditions: v cc = 5 v v e = 2 v v ol = 0.6 v fig.3 switching time vs. forward current 5 012 3456 7911 13 15 v cc = 5 v r l = 1 k ? (t plh ) r l = 4 k ? (t plh ) r l = 350 ? (t plh ) r l = 1 k ? r l = 4 k ? r l = 350 k ? (t phl ) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1 2 3 4 0 20 40 60 80 100 120 20 25 30 35 40 45 50 0 1 2 3 4 5 6 0.001 0.01 0.1 1 10 16 30
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 6 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers t ypical performance curves (continued) fig. 7 pulse width distortion vs. temperature t a ?temperature ( c) t a ?temperature ( c) t a ?temperature ( c) t a ?temperature ( c) t a ?temperature ( c) -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 pwd ?pulse wid th distortio n (ns) t e ?enable pr opagation delay (ns) i oh ?high level output cu rrent ( a) t p ?prop agation de lay (ns) tr/tf rise and fall time (ns) r l = 4 k ? r l = 1 k ? r l = 350 ? f conditions: i = 7.5ma v cc = 5a fig. 8 rise and fall time vs. temperature l r = 4 k ? (tr) conditions: i f = 7.5 ma v cc = 5 v r l = 1 k ? (tr) r l = 350 ? (tr) r l = 1 k ? r l = 4 k ? (tf) r l = 350 ? fig. 9 enable propagation delay vs. temperature rl = 4 k ? (telh) r l = 1 k ? (telh) r l = 350 ? (telh) r l = 350 ? r l = 1 k ? r l = 4 k ? (tehl) fig. 10 switching time vs. temperature rl = 1 k ? tplh rl = 350 ? tplh rl = 4 k ? tplh rl = 1 k ? rl = 4 k ? rl = 350 ? tphl fig. 11 high level output current vs. temperature v cc = 5.5 v conditions: v o = 5.5 v v e = 2.0 v i f = 250 a 0 20 40 60 80 0 100 200 300 400 500 600 0 20 40 60 80 100 120 20 40 60 80 100 120 0 5 10 15 20
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 7 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers t est circuits 47 phl t f i = 7.5 ma 1.5 v 90% 10% 7.5 ma +5v 1.5 v 3.0 v 1.5 v 3 2 1 4 8 7 6 5 4 5 pulse 1 2 3 generator tr = 5ns z = 50 ? o 8 7 6 +5v gnd plh t i = 3.75 ma f out put o (v ) input (i ) f out put (v ) o f t r t cc v out put (v ) o l r c l (i ) input f monitor o z = 50 ? pulse generator tr = 5ns (v ) e input monitor gnd v cc o (v ) out put l r l c (v ) out put o input (v ) e ehl tt elh bypass .1 f bypass .1 f fig. 12 test circuit and waveforms for t plh , t phl, t r and t f fig. 13 test circuit t ehl and t elh
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 8 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers t est circuits (continued) +5v peak 3 2 1 4 8 7 6 5 gnd v cc o (v ) output 350 ? v cm ff v a b pulse gen i f cm v 0v o v 5v switching pos. (a), i = 0 f o v (max) cm 0.5 v o v switching pos. (b), i = 7 .5 ma f h cm l v (min) o bypass .1 f fig. 14 test circuit common mode transient immunity
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 9 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers package dimensions through hole surface mount note: all dimensions are in inches (millimeters) 0.4" lead spacing 8-pin dip ?land pattern 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.020 (0.51) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.300 (7.62) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 15 max pin 1 id. seating p lane lead coplanarity : 0.004 (0.10) max 0.270 (6.86) 0.250 (6.35) 0.390 (9.91) 0.370 (9.40) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) typ 0.020 (0.51) min 0.070 (1.78) 0.045 (1.14) 0.300 (7.62) typ 0.405 (10.30) max. 0.315 (8.00) min 0.045 (1.14) 32 1 4 567 8 0.016 (0.41) 0.008 (0.20) pin 1 id. 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.004 (0.10) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.400 (10.16) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 0 to 15 pin 1 id. seating plane 0.070 (1.78) 0.060 (1.52) 0.030 (0.76) 0.100 (2.54) 0.295 (7.49) 0.415 (10.54)
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 10 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers ordering information marking information option example part number description s 6n137s surface mount lead bend sd 6n137sd surface mount; tape and reel w 6n137w 0.4" lead spacing v 6n137v vde0884 wv 6n137wv vde0884; 0.4 lead spacing sv 6n137sv vde0884; surface mount sdv 6n137sdv vde0884; surface mount; tape and reel 1 2 6 4 3 5 de?itions 1f airchild logo 2d e vice number 3 vde mark (note: only appears on parts ordered with vde option ? see order entry table) 4t wo digit year code, e.g., ?3 5t wo digit work week ranging from ?1 to ?3 6 assembly package code 2601 t1 yy xx v
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 11 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers t ape speci?ations re?w pro?e 4.0 0.1 1.55 0.05 user direction of feed 4.0 0.1 1.75 0.10 7.5 0.1 16.0 0.3 12.0 0.1 0.30 0.05 13.2 0.2 4.90 0.20 0.1 ma x 10.30 0.20 10.30 0.20 1.6 0.1 ? peak reflow temperature: 225 c (package surface temperature) ? time of temperature higher than 183 c for 60?50 seconds ? one time soldering reflow is recommended 215 c, 10?0 s 225 c peak ti me (minute) 0 300 250 200 150 100 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 temperature (?) time above 183 c, 60?50 sec ramp up = 3 c/sec
?005 fairchild semiconductor corporation www.fairchildsemi.com 6n137, hcpl2601, hcpl2611, hcpl2630, hcpl2631 rev. 1.0.8 12 tradem arks th e following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global subsidiaries ,and is not in tended to be an exhaustive list of all such trademarks. a ccupower auto-spm build it now coreplus corepower crossvolt ctl cu rrent transfer logic deuxpeed dual cool ecospark e fficientmax esbc fair child fairchild semiconductor fa ct quiet series fact f ast fa stvcore fetbench flashwriter * fps f-pfs frfet global power resource sm green fps green fps e-series g max gto in tellimax isoplanar me gabuck mi crocoupler microfet mi cropak mi cropak2 m illerdrive moti onmax moti on-spm optohit optologic op toplanar pdp spm powe r-spm po we rtrench powerxs pr ogrammable active droop qfet qs quiet series r apidconfigure savi ng our world ,1mw/w/kwatatime si gnalwise sma rtmax smart start spm stealth s uperfet supe rsot -3 s upersot -6 s upersot -8 s upremos syncfet sy nc-lock * th ep ower franchise th er ight technology for your success tinyb oost tinybuck tiny calc ti nylogic tinyopto tinypower tinypwm tinywire trifault detect t ruecurrent * serdes uhc ultra frfet unifet vcx vi sualmax xs *t rademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers t hese products. li fe support policy fa i rchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are in tended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance wi th instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. an ti -counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external websi te, www.fairchildsemi.com, under sales support. c ounterfeiting of semiconductor parts is a growing problem in the industry. all manufacturers of semiconductor products are experiencing counterf eiting of their parts. cu stomers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, faile da pplications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our customers from the proli feration of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from authorized fairchi ld distribu tors who are lis ted by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchild distributors are ge nuine parts, have full traceability, meet fairchild's quality standards for handling and storage and provide access to fairchild's full range of up-to-date technica land product information. fairchild and our authorized distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. fairc hild will not provide any warranty coverage or other assistance for parts bought from unauthorized sources. fairchild is committed to combat this global problem and encou rage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions defi nition of terms da tasheet identification product st atus definition ad vance information formative / in design datasheet contains the design specifi cations for product development. s pecifications may change in any manner without notice. pr eliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild se mi conductor reserves the right to make changes at any time without notice to improve design. no i dentification needed full production datasheet contains final specifications. fairchi ld semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. th e datasheet is for reference information only. rev. i51 single-channel: 6n137, hcpl2601, hcpl2611 dual-channel: hcpl2630, hcpl2631 ?high speed 10mbit/s logic gate optocouplers

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